Hi Eric,
On Thu, 28 May 2020 at 08:50, Eric FINCO via TSC < tsc@lists.trustedfirmware.org> wrote:
Hi TF-TSC folks,
I was on vacation last week so not able to join the TSC last week.
ST raised a question during the TF-M open forum today concerning the min number of MPU descriptors (= min mumber of regions) to be supported in the SoC especially for of level 3 isolation support.
Furthermore, putting it in perspective with the “measurement” API introduced in the HAL proposal presented in the open forum, one can extend the question: Do you think the TF-M TSC shall issue some recommendation for the minimal Hw configuration required for different features ?
This is something that the TSC should be able to do, but I wonder whether this isn't already covered in various specifications etc created by Arm the last couple of years. I'm thinking about for example TBSA-M that is part of PSA. If MPU descriptors aren't already mentioned, then we could ask to get it added.
Somehow, small profile memory footprint is also pointing in the direction.
There was a positive feedback from Ken (Liu) during the open forum slot but it could make sense to have the TSC reviewing and approving such thing. What do you think ?
Regards,
Eric Finco
Regards, Joakim
Hi Joakim,
Indeed the TBSA_v8M document is referring to the Trustzone for ARMv8-M (section 4 of the document) and indicate the mechanism presents to defined the regions but it also states “the number of regions is defined by the chip designer”. More globally, the TBSA_v8M is presenting the hardware system requirements and the different elements involved to comply with PSA but with quantifying these elements. Furthermore to my understanding the set of PSA documents does not enforce TF-M implementation while the point here is related to the min config for different TF-M config (in the case proposed, the config defined by the isolation level and more specially the level 3 isolation) accordingly I think such information should come from TF-M documentation and not from PSA documents.
Regards,
Eric Finco
[Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: logo_big5] Eric FINCO | Tel: +33 (0)2 4402 7154 MDG | Technical Specialist
From: Joakim Bech joakim.bech@linaro.org Sent: vendredi 29 mai 2020 09:27 To: Eric FINCO eric.finco@st.com Cc: tsc@lists.trustedfirmware.org Subject: Re: [TF-TSC] TF-M hw min requirement in particular for the number of MPU regions
Hi Eric, On Thu, 28 May 2020 at 08:50, Eric FINCO via TSC <tsc@lists.trustedfirmware.orgmailto:tsc@lists.trustedfirmware.org> wrote: Hi TF-TSC folks,
I was on vacation last week so not able to join the TSC last week. ST raised a question during the TF-M open forum today concerning the min number of MPU descriptors (= min mumber of regions) to be supported in the SoC especially for of level 3 isolation support. Furthermore, putting it in perspective with the “measurement” API introduced in the HAL proposal presented in the open forum, one can extend the question: Do you think the TF-M TSC shall issue some recommendation for the minimal Hw configuration required for different features ? This is something that the TSC should be able to do, but I wonder whether this isn't already covered in various specifications etc created by Arm the last couple of years. I'm thinking about for example TBSA-M that is part of PSA. If MPU descriptors aren't already mentioned, then we could ask to get it added.
Somehow, small profile memory footprint is also pointing in the direction. There was a positive feedback from Ken (Liu) during the open forum slot but it could make sense to have the TSC reviewing and approving such thing. What do you think ?
Regards,
Eric Finco
Regards, Joakim
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Eric FINCO -
Joakim Bech