Hi TF-TSC folks,
I was on vacation last week so not able to join the TSC last week. ST raised a question during the TF-M open forum today concerning the min number of MPU descriptors (= min mumber of regions) to be supported in the SoC especially for of level 3 isolation support. Furthermore, putting it in perspective with the "measurement" API introduced in the HAL proposal presented in the open forum, one can extend the question: Do you think the TF-M TSC shall issue some recommendation for the minimal Hw configuration required for different features ? Somehow, small profile memory footprint is also pointing in the direction. There was a positive feedback from Ken (Liu) during the open forum slot but it could make sense to have the TSC reviewing and approving such thing. What do you think ?
Regards,
Eric Finco
[Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: Description: logo_big5] Eric FINCO | Tel: +33 (0)2 4402 7154 MDG | Technical Specialist
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