Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1756/

Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2458994 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2458995 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2458996 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2458997 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2458998 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2458999 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2459000 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2459001 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2459002 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2459003 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459004 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2459005 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2459006 MUSCA_B1_GCC_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459007 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459008 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459009 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2459010 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459011 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2459013 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459012 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459014 MUSCA_B1_ARMCLANG_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2459015 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459016 MUSCA_B1_GCC_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2459017 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459018 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2459019 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2459020 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459021 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459022 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459023 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2459024 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459025 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2459026 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2459027 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459028 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2459029 MUSCA_B1_ARMCLANG_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2459030 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459031 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2459032 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2459033 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2459034 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459035 MUSCA_B1_GCC_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2459036 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2459037 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2459038 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2459039 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2459040 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2459041

For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1756/artifact/test_results.cs...