Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1747/

Failed Jobs: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453457 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2453458 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2453459 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453460 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2453461 MUSCA_B1_ARMCLANG_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2453462 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2453463 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453464 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453465 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453466 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453467 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2453468 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453469 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453470 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453471 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453472 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2453475 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453476 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2453473 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453474 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453477 MUSCA_B1_GCC_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453478 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2453479 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2453480 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453481 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453482 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2453483 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453484 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453485 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2453486 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453487 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453488 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453489 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453490 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453491 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453492 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2453495 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453496 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453493 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2453494 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2453499 MUSCA_B1_ARMCLANG_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453497 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2453498 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2453500 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2453502 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2453503 MUSCA_B1_GCC_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2453504 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2453501

For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1747/artifact/test_results.cs...