Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/2129/

Failed Jobs: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2697848 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2697849 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2697850 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2697851 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2697852 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2697853 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2697854 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2697855 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2697856 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2697857

For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/2129/artifact/test_results.cs...