Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1751/

Failed Jobs: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456007 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456008 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456009 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456010 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456011 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456012 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456013 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456014 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456015 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456016 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456017 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456018 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456019 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456020 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456021 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456022 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456023 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456024 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456025 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456026 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456027 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456028 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456029 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456030 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456031 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456032 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456033 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456034 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456035 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456036 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456037 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456038 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456039 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456040 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456041 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456042 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456043 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456044 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456045 MUSCA_B1_ARMCLANG_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456046 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456048 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456049 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456047 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456050 MUSCA_B1_GCC_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456051 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456052 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456053 MUSCA_B1_GCC_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456054

For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1751/artifact/test_results.cs...