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Job tf-m-nightly test 1754 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1754/ Failed Jobs: MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457881 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457882 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457883 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457884 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457885 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457886 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457887 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457888 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457889 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457890 MUSCA_B1_GCC_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457891 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457892 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457893 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457894 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457895 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457896 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457897 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457898 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457899 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457900 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457901 MUSCA_B1_GCC_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457902 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457903 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457904 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457905 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457906 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457907 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457908 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457909 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457910 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457911 MUSCA_B1_GCC_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457912 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457913 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457914 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457915 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457916 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457919 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457917 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457918 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457920 MUSCA_B1_GCC_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457921 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457922 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457923 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457924 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457925 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457926 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457927 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457928 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1754/artifact/test_results.c…

1 year, 10 months

1
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Job tf-m-nightly test 1753 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1753/ Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457223 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457224 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457225 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457226 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457227 MUSCA_B1_GCC_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457228 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457229 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457230 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457231 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457232 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457233 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457234 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457235 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457236 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457237 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457238 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457239 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457240 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457241 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457242 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457243 MUSCA_B1_GCC_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457244 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457245 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457246 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457247 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457248 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457249 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457250 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457251 MUSCA_B1_GCC_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457252 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457253 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457254 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457255 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457256 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457257 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457258 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457259 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457260 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457261 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457262 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457263 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457264 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457265 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2457266 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457267 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457268 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457269 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457270 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1753/artifact/test_results.c…

1 year, 10 months

1
0
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Job tf-m-nightly build 1753 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1753/ Failed Jobs: AN521_ARMCLANG_3_ATTEST_Minsizerel_BL2 http://ci.trustedfirmware.org/job/tf-m-build-config/1510472/ For detailed build results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1753/artifact/build_results.…

1 year, 10 months

1
0
0 0

Job tf-m-nightly test 1752 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1752/ Failed Jobs: MUSCA_B1_ARMCLANG_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456623 MUSCA_B1_GCC_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456621 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456622 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456624 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456625 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456627 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456628 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456629 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456630 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456631 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456632 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456633 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456634 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456635 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456636 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456637 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456638 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456639 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456640 MUSCA_B1_GCC_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456641 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456642 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456643 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456644 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456645 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456646 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456647 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456648 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456649 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456650 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456651 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456652 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456653 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456654 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456655 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456656 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456657 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456658 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456659 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456660 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456661 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456663 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456664 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456662 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456665 MUSCA_B1_GCC_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456667 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456666 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456668 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456669 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1752/artifact/test_results.c…

1 year, 10 months

1
0
0 0

Job tf-m-nightly test 1751 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1751/ Failed Jobs: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456007 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456008 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456009 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456010 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456011 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456012 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456013 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456014 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456015 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456016 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456017 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456018 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456019 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456020 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456021 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456022 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456023 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456024 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456025 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456026 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456027 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456028 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456029 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456030 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456031 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456032 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456033 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456034 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456035 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456036 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456037 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2456038 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456039 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456040 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456041 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456042 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456043 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456044 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456045 MUSCA_B1_ARMCLANG_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456046 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2456048 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2456049 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2456047 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2456050 MUSCA_B1_GCC_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456051 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2456052 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2456053 MUSCA_B1_GCC_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2456054 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1751/artifact/test_results.c…

1 year, 10 months

1
0
0 0

Job tf-m-nightly build 1751 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1751/ Failed Jobs: MUSCA_S1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC http://ci.trustedfirmware.org/job/tf-m-build-config/1509017/ For detailed build results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1751/artifact/build_results.…

1 year, 10 months

1
0
0 0

Job tf-m-nightly test 1750 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1750/ Failed Jobs: stm32h573i_dk_GCC_1_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455390 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455368 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455369 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2455370 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455371 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2455372 MUSCA_B1_GCC_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455373 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455374 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2455375 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2455376 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455377 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455378 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2455379 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455380 MUSCA_B1_GCC_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455381 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455382 MUSCA_B1_GCC_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455383 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455384 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455385 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455386 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455387 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2455388 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455389 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455391 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455392 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2455393 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2455394 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455395 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2455396 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455397 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2455398 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455399 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2455400 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455401 MUSCA_B1_GCC_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2455402 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2455403 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2455404 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455405 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2455406 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455407 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455408 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2455409 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA https://tf.validation.linaro.org/scheduler/job/2455410 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2455411 MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2455412 MUSCA_B1_GCC_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2455413 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2455414 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2455415 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2455416 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1750/artifact/test_results.c…

1 year, 10 months

1
0
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Job tf-m-nightly build 1750 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1750/ Failed Jobs: CS300_AN552_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON http://ci.trustedfirmware.org/job/tf-m-build-config/1508210/ For detailed build results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1750/artifact/build_results.…

1 year, 10 months

1
0
0 0

Job tf-m-nightly test 1749 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1749/ Failed Jobs: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454759 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2454760 MUSCA_B1_ARMCLANG_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2454761 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2454763 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454764 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454765 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454766 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454767 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454768 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454769 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454770 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454771 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454772 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454773 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454774 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454775 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454776 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2454777 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2454778 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454779 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454782 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454780 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454781 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454783 MUSCA_B1_ARMCLANG_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2454784 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454785 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454786 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454787 MUSCA_B1_GCC_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2454788 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2454789 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454790 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2454791 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454792 MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454793 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454794 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454795 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2454796 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454797 MUSCA_B1_ARMCLANG_3_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2454798 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454799 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2454800 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2454801 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454802 MUSCA_B1_GCC_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2454803 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2454804 MUSCA_B1_GCC_1_Debug_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2454805 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2454806 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2454807 For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1749/artifact/test_results.c…

1 year, 10 months

1
0
0 0

Job tf-m-nightly build 1749 fail

by ci_notify＠trustedfirmware.org

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1749/ Failed Jobs: MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF http://ci.trustedfirmware.org/job/tf-m-build-config/1507082/ For detailed build results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1749/artifact/build_results.…

1 year, 10 months

1
0
0 0

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