- TF-M-ci-notifications - lists.trustedfirmware.org

LAVA notification for Test Job 2806560 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC_196146_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2806560 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2806560 Test error: lava-test-monitor timed out after 1200 seconds Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC_196146_musca-b Submitted: 2025-09-26 00:04:19 (+0000 UTC) Started: 2025-09-26 00:48:15 (+0000 UTC) Finished: 2025-09-26 01:14:23 (+0000 UTC) Duration: 0:26:08 -- LAVA Linaro Automated Validation Architecture

7 hours, 30 minutes

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LAVA notification for Test Job 2806289 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC_195957_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2806289 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2806289 Test error: lava-test-monitor timed out after 1200 seconds Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC_195957_musca-b Submitted: 2025-09-25 17:47:51 (+0000 UTC) Started: 2025-09-25 19:46:05 (+0000 UTC) Finished: 2025-09-25 20:12:13 (+0000 UTC) Duration: 0:26:07 -- LAVA Linaro Automated Validation Architecture

12 hours, 32 minutes

1
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LAVA notification for Test Job 2806188 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF_195915_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2806188 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2806188 Job error: wait-musca-path timed out after 712 seconds Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF_195915_musca-b Submitted: 2025-09-25 17:38:45 (+0000 UTC) Started: 2025-09-25 18:29:41 (+0000 UTC) Finished: 2025-09-25 18:41:42 (+0000 UTC) Duration: 0:12:01 -- LAVA Linaro Automated Validation Architecture

14 hours, 2 minutes

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Job tf-m-nightly build 136 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/136/ Failed Jobs: RSE_TC4_GCC_3_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195662/ RSE_TC4_GCC_2_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195690/ RSE_TC4_GCC_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195711/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195743/ RSE_TC4_GCC_3_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195862/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195900/ RSE_TC4_GCC_2_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195902/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195903/ RSE_TC4_GCC_2_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195907/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195974/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195981/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/196007/ RSE_RDV3R1_GCC_2_Release_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/195515/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195696/ RSE_TC4_GCC_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195750/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195854/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195941/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195942/ RSE_TC4_GCC_3_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195993/ RSE_RDV3R1_GCC_1_Release_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/195502/ RSE_RDV3R1_GCC_1_Debug_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/195544/ RSE_TC4_GCC_2_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195586/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195701/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195709/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195793/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195935/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195589/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195685/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195695/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195714/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195815/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195708/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195764/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195581/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195893/ RSE_RDV3R1_GCC_2_Debug_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/195638/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195534/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195553/ RSE_TC4_GCC_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195868/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195703/ RSE_TC4_GCC_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195953/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/195847/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195615/ RSE_TC4_GCC_3_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195653/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/195892/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/195830/ For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/136/artifact/build_results.… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

14 hours, 52 minutes

1
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0 0

LAVA notification for Test Job 2806029 b_u585i_iot02a_ARMCLANG_2_RegS_RegNS_Release_BL2_195402_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2806029 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2806029 Infrastructure error: Unable to reboot: '/usr/local/lab-scripts/stm32_tfm_flasher.sh -c reset -s 000C001E4D46501220383832' failed Device details: Hostname: b-u585i-iot02a-01 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_ARMCLANG_2_RegS_RegNS_Release_BL2_195402_b-u585i-iot02a Submitted: 2025-09-25 15:34:36 (+0000 UTC) Started: 2025-09-25 15:34:38 (+0000 UTC) Finished: 2025-09-25 15:35:07 (+0000 UTC) Duration: 0:00:29 -- LAVA Linaro Automated Validation Architecture

17 hours, 9 minutes

1
0
0 0

LAVA notification for Test Job 2805484 b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_194406_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2805484 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2805484 Infrastructure error: Unable to reboot: '/usr/local/lab-scripts/stm32_tfm_flasher.sh -c reset -s 0032001E4D46501220383832' failed Device details: Hostname: b-u585i-iot02a-03 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_194406_b-u585i-iot02a Submitted: 2025-09-24 23:48:32 (+0000 UTC) Started: 2025-09-24 23:48:34 (+0000 UTC) Finished: 2025-09-24 23:49:01 (+0000 UTC) Duration: 0:00:26 -- LAVA Linaro Automated Validation Architecture

1 day, 8 hours

1
0
0 0

Job tf-m-nightly test 134 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/134/ Failed Jobs: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2805066 AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2_LARGE https://tf.validation.linaro.org/scheduler/job/2805068 For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/134/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

1 day, 21 hours

1
0
0 0

LAVA notification for Test Job 2805066 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_155632_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2805066 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2805066 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/155632//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-05 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_155632_musca-b Submitted: 2025-09-24 11:23:50 (+0000 UTC) Started: 2025-09-24 11:23:50 (+0000 UTC) Finished: 2025-09-24 11:23:51 (+0000 UTC) Duration: 0:00:01 -- LAVA Linaro Automated Validation Architecture

1 day, 21 hours

1
0
0 0

Job tf-m-nightly build 134 fail

by svc_openci_enginfra＠arm.com

1 day, 21 hours

1
0
0 0

LAVA notification for Test Job 2804875 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC_192477_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2804875 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2804875 Test error: lava-test-monitor timed out after 1200 seconds Device details: Hostname: musca-b-05 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC_192477_musca-b Submitted: 2025-09-23 23:59:12 (+0000 UTC) Started: 2025-09-24 00:19:05 (+0000 UTC) Finished: 2025-09-24 00:45:12 (+0000 UTC) Duration: 0:26:07 -- LAVA Linaro Automated Validation Architecture

2 days, 3 hours

1
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0 0

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