- TF-M-ci-notifications - lists.trustedfirmware.org

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/71/ Failed Jobs: RSE_TC4_GCC_1_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103928/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103954/ RSE_TC4_GCC_2_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103935/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103953/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103931/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103947/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103930/ RSE_TC4_GCC_1_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103926/ RSE_TC4_GCC_3_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103923/ RSE_TC4_GCC_3_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103925/ RSE_TC4_GCC_3_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103927/ RSE_TC4_GCC_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103932/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103936/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103937/ RSE_TC4_GCC_2_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103938/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103939/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103948/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103949/ RSE_TC4_GCC_2_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103951/ RSE_TC4_GCC_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103933/ RSE_TC4_GCC_3_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103942/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103929/ lpcxpresso55s69_GCC_2_Relwithdebinfo_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/103943/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103940/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103945/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103934/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103941/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103944/ lpcxpresso55s69_GCC_2_RegS_RegNS_Relwithdebinfo_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/103924/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103946/ RSE_TC4_GCC_2_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/103950/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_RSE_PROVISIONING_ASYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/103952/ For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/71/artifact/build_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

3 days, 2 hours

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LAVA notification for Test Job 2775229 stm32l562e_dk_GCC_3_RegBL2_RegS_RegNS_Release_BL2_CRYPTO_OFF_103973_stm32l562e-dk

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2775229 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2775229 Infrastructure error: Connection closed Device details: Hostname: stm32l562e-dk-02 Type: stm32l562e-dk Owner: None Worker: w2 Job details: Priority: Medium Description: stm32l562e_dk_GCC_3_RegBL2_RegS_RegNS_Release_BL2_CRYPTO_OFF_103973_stm32l562e-dk Submitted: 2025-07-28 12:50:31 (+0000 UTC) Started: 2025-07-28 12:50:32 (+0000 UTC) Finished: 2025-07-28 12:51:58 (+0000 UTC) Duration: 0:01:26 -- LAVA Linaro Automated Validation Architecture

3 days, 2 hours

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LAVA notification for Test Job 2775223 stm32l562e_dk_GCC_3_RegBL2_RegS_RegNS_Release_BL2_CRYPTO_OFF_103882_stm32l562e-dk

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2775223 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2775223 Infrastructure error: Connection closed Device details: Hostname: stm32l562e-dk-02 Type: stm32l562e-dk Owner: None Worker: w2 Job details: Priority: Medium Description: stm32l562e_dk_GCC_3_RegBL2_RegS_RegNS_Release_BL2_CRYPTO_OFF_103882_stm32l562e-dk Submitted: 2025-07-28 12:38:40 (+0000 UTC) Started: 2025-07-28 12:38:41 (+0000 UTC) Finished: 2025-07-28 12:40:18 (+0000 UTC) Duration: 0:01:36 -- LAVA Linaro Automated Validation Architecture

3 days, 3 hours

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LAVA notification for Test Job 2775213 stm32l562e_dk_ARMCLANG_1_RegS_RegNS_Release_BL2_CRYPTO_OFF_103879_stm32l562e-dk

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2775213 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2775213 Infrastructure error: Connection closed Device details: Hostname: stm32l562e-dk-02 Type: stm32l562e-dk Owner: None Worker: w2 Job details: Priority: Medium Description: stm32l562e_dk_ARMCLANG_1_RegS_RegNS_Release_BL2_CRYPTO_OFF_103879_stm32l562e-dk Submitted: 2025-07-28 11:58:54 (+0000 UTC) Started: 2025-07-28 11:58:55 (+0000 UTC) Finished: 2025-07-28 12:00:30 (+0000 UTC) Duration: 0:01:34 -- LAVA Linaro Automated Validation Architecture

3 days, 3 hours

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LAVA notification for Test Job 2774852 MUSCA_B1_ARMCLANG_2_Debug_BL2_TEST_CBOR_102972_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774852 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774852 Job error: wait-musca-path timed out after 712 seconds Device details: Hostname: musca-b-05 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_Debug_BL2_TEST_CBOR_102972_musca-b Submitted: 2025-07-27 07:51:35 (+0000 UTC) Started: 2025-07-27 08:20:42 (+0000 UTC) Finished: 2025-07-27 08:32:44 (+0000 UTC) Duration: 0:12:01 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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LAVA notification for Test Job 2774870 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_80170_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774870 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774870 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/80170//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_80170_musca-b Submitted: 2025-07-27 07:52:19 (+0000 UTC) Started: 2025-07-27 08:28:52 (+0000 UTC) Finished: 2025-07-27 08:28:53 (+0000 UTC) Duration: 0:00:00 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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LAVA notification for Test Job 2774867 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2_TEST_CBOR_80169_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774867 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774867 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/80169//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2_TEST_CBOR_80169_musca-b Submitted: 2025-07-27 07:51:58 (+0000 UTC) Started: 2025-07-27 08:28:50 (+0000 UTC) Finished: 2025-07-27 08:28:51 (+0000 UTC) Duration: 0:00:00 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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LAVA notification for Test Job 2774866 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_TEST_CBOR_80157_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774866 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774866 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/80157//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_TEST_CBOR_80157_musca-b Submitted: 2025-07-27 07:51:49 (+0000 UTC) Started: 2025-07-27 08:28:48 (+0000 UTC) Finished: 2025-07-27 08:28:49 (+0000 UTC) Duration: 0:00:00 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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LAVA notification for Test Job 2774865 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_80161_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774865 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774865 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/80161//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_80161_musca-b Submitted: 2025-07-27 07:51:47 (+0000 UTC) Started: 2025-07-27 08:28:46 (+0000 UTC) Finished: 2025-07-27 08:28:47 (+0000 UTC) Duration: 0:00:00 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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LAVA notification for Test Job 2774853 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_TEST_CBOR_80171_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2774853 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2774853 Job error: Invalid job data: ["Resource unavailable at 'https://ci.trustedfirmware.org/job/tf-m-lava-submit/80171//artifact/ci_build/spe/bin/tfm.hex' (404)"] Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_TEST_CBOR_80171_musca-b Submitted: 2025-07-27 07:51:36 (+0000 UTC) Started: 2025-07-27 08:21:16 (+0000 UTC) Finished: 2025-07-27 08:21:17 (+0000 UTC) Duration: 0:00:00 -- LAVA Linaro Automated Validation Architecture

4 days, 7 hours

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TF-M-ci-notifications