[TF-M-ci-notifications] Job tf-m-nightly test 1754 fail

Check console output at http://ci.trustedfirmware.org/job/tf-m-nightly/1754/

Failed Jobs: MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457881 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457882 MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457883 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457884 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457885 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457886 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457887 MUSCA_B1_GCC_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457888 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457889 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457890 MUSCA_B1_GCC_2_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457891 MUSCA_B1_GCC_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457892 MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457893 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457894 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457895 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457896 MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457897 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457898 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457899 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457900 MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457901 MUSCA_B1_GCC_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457902 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457903 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457904 MUSCA_B1_ARMCLANG_2_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457905 MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457906 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457907 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457908 MUSCA_B1_GCC_3_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457909 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457910 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457911 MUSCA_B1_GCC_1_Debug_BL2 https://tf.validation.linaro.org/scheduler/job/2457912 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457913 MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457914 MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://tf.validation.linaro.org/scheduler/job/2457915 MUSCA_B1_ARMCLANG_1_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457916 MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457919 MUSCA_B1_ARMCLANG_3_Release_BL2 https://tf.validation.linaro.org/scheduler/job/2457917 MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457918 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457920 MUSCA_B1_GCC_2_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457921 MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://tf.validation.linaro.org/scheduler/job/2457922 MUSCA_B1_GCC_2_Release_BL2_MEDIUM_PSOFF https://tf.validation.linaro.org/scheduler/job/2457923 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2457924 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457925 MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457926 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://tf.validation.linaro.org/scheduler/job/2457927 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://tf.validation.linaro.org/scheduler/job/2457928

For detailed test results please refer to http://ci.trustedfirmware.org/job/tf-m-nightly/1754/artifact/test_results.cs...