- TF-M-ci-notifications - lists.trustedfirmware.org

LAVA notification for Test Job 2938071 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_TEST_CBOR_527625_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2938071 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2938071 Job error: Invalid job data: ["Unable to get 'https://ci.trustedfirmware.org/job/tf-m-build-config/527625//artifact/ci_build/spe/bin/tfm.hex': HTTPSConnectionPool(host='ci.trustedfirmware.org', port=443): Max retries exceeded with url: /job/tf-m-build-config/527625//artifact/ci_build/spe/bin/tfm.hex (Caused by ResponseError('too many 503 error responses'))"] Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_TEST_CBOR_527625_musca-b Submitted: 2026-04-26 12:56:49 (+0000 UTC) Started: 2026-04-26 13:03:07 (+0000 UTC) Finished: 2026-04-26 13:04:31 (+0000 UTC) Duration: 0:01:23 -- LAVA Linaro Automated Validation Architecture

2 weeks

1
0
0 0

LAVA notification for Test Job 2937993 MUSCA_B1_GCC_1_Release_BL2_TEST_CBOR_526488_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2937993 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2937993 Job error: Invalid job data: ["Unable to get 'https://ci.trustedfirmware.org/job/tf-m-build-config/526488//artifact/ci_build/spe/bin/tfm.hex': HTTPSConnectionPool(host='ci.trustedfirmware.org', port=443): Max retries exceeded with url: /job/tf-m-build-config/526488//artifact/ci_build/spe/bin/tfm.hex (Caused by ResponseError('too many 503 error responses'))"] Device details: Hostname: musca-b-02 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_Release_BL2_TEST_CBOR_526488_musca-b Submitted: 2026-04-26 07:51:31 (+0000 UTC) Started: 2026-04-26 09:44:43 (+0000 UTC) Finished: 2026-04-26 09:45:35 (+0000 UTC) Duration: 0:00:51 -- LAVA Linaro Automated Validation Architecture

2 weeks

1
0
0 0

LAVA notification for Test Job 2937950 MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_526461_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2937950 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2937950 Job error: Invalid job data: ["Unable to get 'https://ci.trustedfirmware.org/job/tf-m-build-config/526461//artifact/ci_build/spe/bin/tfm.hex': HTTPSConnectionPool(host='ci.trustedfirmware.org', port=443): Max retries exceeded with url: /job/tf-m-build-config/526461//artifact/ci_build/spe/bin/tfm.hex (Caused by ResponseError('too many 503 error responses'))"] Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_526461_musca-b Submitted: 2026-04-26 07:46:53 (+0000 UTC) Started: 2026-04-26 09:10:10 (+0000 UTC) Finished: 2026-04-26 09:11:02 (+0000 UTC) Duration: 0:00:51 -- LAVA Linaro Automated Validation Architecture

2 weeks

1
0
0 0

LAVA notification for Test Job 2937946 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_526140_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2937946 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2937946 Job error: Invalid job data: ["Unable to get 'https://ci.trustedfirmware.org/job/tf-m-build-config/526140//artifact/ci_build/spe/bin/tfm.hex': HTTPSConnectionPool(host='ci.trustedfirmware.org', port=443): Max retries exceeded with url: /job/tf-m-build-config/526140//artifact/ci_build/spe/bin/tfm.hex (Caused by ResponseError('too many 503 error responses'))"] Device details: Hostname: musca-b-02 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_526140_musca-b Submitted: 2026-04-26 07:46:34 (+0000 UTC) Started: 2026-04-26 09:09:33 (+0000 UTC) Finished: 2026-04-26 09:10:40 (+0000 UTC) Duration: 0:01:07 -- LAVA Linaro Automated Validation Architecture

2 weeks

1
0
0 0

LAVA notification for Test Job 2936329 b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_522126_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2936329 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2936329 Infrastructure error: Unable to reboot: '/usr/local/lab-scripts/stm32_tfm_flasher.sh -c reset -s 0031001D4D46501220383832' failed Device details: Hostname: b-u585i-iot02a-02 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_522126_b-u585i-iot02a Submitted: 2026-04-22 14:28:49 (+0000 UTC) Started: 2026-04-22 14:28:50 (+0000 UTC) Finished: 2026-04-22 14:29:17 (+0000 UTC) Duration: 0:00:26 -- LAVA Linaro Automated Validation Architecture

2 weeks, 4 days

1
0
0 0

Job tf-m-nightly test 370 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/370/ Failed Jobs: RSE_TC4_GCC_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3Ch53m3M79xv8t3… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/370/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

2 weeks, 4 days

1
0
0 0

LAVA notification for Test Job 2931687 MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF_517796_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2931687 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2931687 Job error: wait-musca-path timed out after 712 seconds Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF_517796_musca-b Submitted: 2026-04-20 00:09:29 (+0000 UTC) Started: 2026-04-20 02:07:08 (+0000 UTC) Finished: 2026-04-20 02:19:09 (+0000 UTC) Duration: 0:12:01 -- LAVA Linaro Automated Validation Architecture

2 weeks, 6 days

1
0
0 0

Job tf-m-nightly test 366 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/366/ Failed Jobs: RSE_TC4_GCC_3_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3CVlkfCPHYhxNaN… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/366/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

2 weeks, 6 days

1
2
0 0

Job tf-m-nightly build 362 fail

by svc_openci_enginfra＠arm.com

3 weeks, 3 days

1
2
0 0

LAVA notification for Test Job 2926927 b_u585i_iot02a_ARMCLANG_1_RegS_RegNS_Release_BL2_509574_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2926927 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2926927 Infrastructure error: Unable to reboot: '/usr/local/lab-scripts/stm32_tfm_flasher.sh -c reset -s 0032001E4D46501220383832' failed Device details: Hostname: b-u585i-iot02a-03 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_ARMCLANG_1_RegS_RegNS_Release_BL2_509574_b-u585i-iot02a Submitted: 2026-04-16 00:09:41 (+0000 UTC) Started: 2026-04-16 00:09:42 (+0000 UTC) Finished: 2026-04-16 00:10:10 (+0000 UTC) Duration: 0:00:28 -- LAVA Linaro Automated Validation Architecture

3 weeks, 3 days

1
0
0 0

LAVA notification for Test Job 2926705 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF_509555_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2926705 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2926705 Infrastructure error: Flash failure indicated by presence of FAIL.TXT (Details: The hex file cannot be decoded. Checksum calculation failure occurred.) Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF_509555_musca-b Submitted: 2026-04-15 23:47:56 (+0000 UTC) Started: 2026-04-15 23:53:52 (+0000 UTC) Finished: 2026-04-15 23:56:42 (+0000 UTC) Duration: 0:02:50 -- LAVA Linaro Automated Validation Architecture

3 weeks, 3 days

1
0
0 0

Job tf-m-nightly build 351 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/351/ Failed Jobs: CS300_AN552_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490568/ AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490515/ CS300_FVP_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490652/ CS300_AN552_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490659/ AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490578/ CS300_FVP_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490823/ CS300_AN552_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490352/ CS300_AN552_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490392/ CS300_AN552_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490446/ AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490636/ AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490725/ CS300_FVP_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/491050/ AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/491067/ AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490484/ CS300_FVP_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490671/ CS300_FVP_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490957/ CS300_FVP_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490959/ AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490965/ CS300_AN552_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490982/ CS300_FVP_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490921/ CS300_AN552_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490809/ CS300_FVP_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://ci.trustedfirmware.org/job/tf-m-build-config/490814/ AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490869/ CS300_AN552_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON https://ci.trustedfirmware.org/job/tf-m-build-config/490852/ For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/351/artifact/build_results.… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 weeks, 1 day

1
12
0 0

LAVA notification for Test Job 2922755 MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_500726_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2922755 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2922755 Infrastructure error: Flash failure indicated by presence of FAIL.TXT (Details: The hex file cannot be decoded. Checksum calculation failure occurred.) Device details: Hostname: musca-b-04 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_500726_musca-b Submitted: 2026-04-09 23:48:51 (+0000 UTC) Started: 2026-04-10 01:21:23 (+0000 UTC) Finished: 2026-04-10 01:23:53 (+0000 UTC) Duration: 0:02:29 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2921105 stm32wba65i_dk_GCC_1_RegS_RegNS_Release_497637_stm32wba65i-dk1

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2921105 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2921105 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32wba65i-dk1-03 Type: stm32wba65i-dk1 Owner: None Worker: w2 Job details: Priority: Medium Description: stm32wba65i_dk_GCC_1_RegS_RegNS_Release_497637_stm32wba65i-dk1 Submitted: 2026-04-08 19:09:46 (+0000 UTC) Started: 2026-04-08 19:09:47 (+0000 UTC) Finished: 2026-04-08 19:13:08 (+0000 UTC) Duration: 0:03:20 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2921099 stm32h573i_dk_ARMCLANG_1_RegS_RegNS_Release_BL2_498054_stm32h573i-dk

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2921099 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2921099 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32h573i-dk-02 Type: stm32h573i-dk Owner: None Worker: w2 Job details: Priority: Medium Description: stm32h573i_dk_ARMCLANG_1_RegS_RegNS_Release_BL2_498054_stm32h573i-dk Submitted: 2026-04-08 19:09:21 (+0000 UTC) Started: 2026-04-08 19:09:22 (+0000 UTC) Finished: 2026-04-08 19:12:54 (+0000 UTC) Duration: 0:03:31 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2920635 b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_496564_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2920635 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2920635 Infrastructure error: Unable to reboot: '/usr/local/lab-scripts/stm32_tfm_flasher.sh -c reset -s 000C001E4D46501220383832' failed Device details: Hostname: b-u585i-iot02a-01 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_496564_b-u585i-iot02a Submitted: 2026-04-08 14:41:48 (+0000 UTC) Started: 2026-04-08 14:41:49 (+0000 UTC) Finished: 2026-04-08 14:42:19 (+0000 UTC) Duration: 0:00:30 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2918046 MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_493488_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2918046 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2918046 Infrastructure error: Flash failure indicated by presence of FAIL.TXT (Details: The hex file cannot be decoded. Checksum calculation failure occurred.) Device details: Hostname: musca-b-05 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_493488_musca-b Submitted: 2026-04-05 23:48:19 (+0000 UTC) Started: 2026-04-06 00:17:39 (+0000 UTC) Finished: 2026-04-06 00:19:27 (+0000 UTC) Duration: 0:01:47 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2917983 MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_493116_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2917983 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2917983 Job error: wait-musca-path timed out after 708 seconds Device details: Hostname: musca-b-02 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_493116_musca-b Submitted: 2026-04-05 23:44:30 (+0000 UTC) Started: 2026-04-05 23:44:31 (+0000 UTC) Finished: 2026-04-05 23:56:33 (+0000 UTC) Duration: 0:12:02 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

LAVA notification for Test Job 2917691 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_492364_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2917691 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2917691 Infrastructure error: Flash failure indicated by presence of FAIL.TXT (Details: The hex file cannot be decoded. Checksum calculation failure occurred.) Device details: Hostname: musca-b-02 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_492364_musca-b Submitted: 2026-04-05 16:31:27 (+0000 UTC) Started: 2026-04-05 16:37:24 (+0000 UTC) Finished: 2026-04-05 16:41:37 (+0000 UTC) Duration: 0:04:13 -- LAVA Linaro Automated Validation Architecture

1 month

1
0
0 0

Job tf-m-nightly test 351 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/351/ Failed Jobs: AN521_GCC_3_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916751 AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916752 AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916753 AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916748 AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916749 AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tf.validation.linaro.org/scheduler/job/2916750 For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/351/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

1 month

1
0
0 0

Job tf-m-nightly test 345 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/345/ Failed Jobs: AN521_GCC_1_RegNS_Debug_BL2_ERPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3Bb4nwrHP07x2GN… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/345/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

1 month, 1 week

1
4
0 0

LAVA notification for Test Job 2911467 stm32wba65i_dk_GCC_1_RegS_RegNS_Release_SMALL_484055_stm32wba65i-dk1

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2911467 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2911467 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32wba65i-dk1-01 Type: stm32wba65i-dk1 Owner: None Worker: w2 Job details: Priority: Medium Description: stm32wba65i_dk_GCC_1_RegS_RegNS_Release_SMALL_484055_stm32wba65i-dk1 Submitted: 2026-03-29 05:34:21 (+0000 UTC) Started: 2026-03-29 05:34:22 (+0000 UTC) Finished: 2026-03-29 05:38:07 (+0000 UTC) Duration: 0:03:45 -- LAVA Linaro Automated Validation Architecture

1 month, 1 week

1
0
0 0

LAVA notification for Test Job 2911466 stm32wba65i_dk_ARMCLANG_1_RegS_RegNS_Release_SMALL_484045_stm32wba65i-dk1

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2911466 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2911466 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32wba65i-dk1-02 Type: stm32wba65i-dk1 Owner: None Worker: w2 Job details: Priority: Medium Description: stm32wba65i_dk_ARMCLANG_1_RegS_RegNS_Release_SMALL_484045_stm32wba65i-dk1 Submitted: 2026-03-29 05:34:21 (+0000 UTC) Started: 2026-03-29 05:34:22 (+0000 UTC) Finished: 2026-03-29 05:38:06 (+0000 UTC) Duration: 0:03:43 -- LAVA Linaro Automated Validation Architecture

1 month, 1 week

1
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LAVA notification for Test Job 2911465 stm32wba65i_dk_GCC_1_RegS_RegNS_Release_SMALL_484055_stm32wba65i-dk1

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2911465 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2911465 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32wba65i-dk1-02 Type: stm32wba65i-dk1 Owner: None Worker: w2 Job details: Priority: Medium Description: stm32wba65i_dk_GCC_1_RegS_RegNS_Release_SMALL_484055_stm32wba65i-dk1 Submitted: 2026-03-29 05:29:21 (+0000 UTC) Started: 2026-03-29 05:30:36 (+0000 UTC) Finished: 2026-03-29 05:34:12 (+0000 UTC) Duration: 0:03:36 -- LAVA Linaro Automated Validation Architecture

1 month, 1 week

1
0
0 0

LAVA notification for Test Job 2911460 stm32wba65i_dk_ARMCLANG_1_RegS_RegNS_Release_SMALL_484045_stm32wba65i-dk1

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2911460 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2911460 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: stm32wba65i-dk1-02 Type: stm32wba65i-dk1 Owner: None Worker: w2 Job details: Priority: Medium Description: stm32wba65i_dk_ARMCLANG_1_RegS_RegNS_Release_SMALL_484045_stm32wba65i-dk1 Submitted: 2026-03-29 05:26:50 (+0000 UTC) Started: 2026-03-29 05:26:52 (+0000 UTC) Finished: 2026-03-29 05:30:35 (+0000 UTC) Duration: 0:03:42 -- LAVA Linaro Automated Validation Architecture

1 month, 1 week

1
0
0 0

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TF-M-ci-notifications