Hi,

The Base Platform Fast Model from Arm provides a SMMUv3TestEngine component with a control region at 0x002bfe0000-0x002bffFFFF. This component is a traffic generator that acts as a (secure) device upstream of the SMMUv3. We developed the test in the tf-a-tests repo by leveraging this test engine after referring to some documentation in files internal to Arm. Unfortunately, I could not find any detailed upstream documentation for this module.

Software running at lower ELs such as S-EL1 can generate memory transactions on the bus, by writing to the control pages, to mimic workloads such as memcpy. Is there anything that you are looking for in particular with this testengine?

Thanks, Madhukar

-----Original Message----- From: Chenxu Wang via TF-A-Tests tf-a-tests@lists.trustedfirmware.org Sent: Friday, December 16, 2022 9:55 AM To: tf-a-tests@lists.trustedfirmware.org Subject: [Tf-a-tests] Any manuals for SMMUv3 Test Engine?

Hi All,

I find that in spm/cactus/cactus_tests/smmuv3_test_engine.h, the tf-a-tests clearly shows some MMIO interfaces for the SMMUv3 Test Engine. But, I need help finding a manual about these MMIO interfaces. For example, in this .h file, it says the offset of the start address is in 0x28 (BEGIN_OFF), but I cannot find which manual defines it. It refers to the "SMMUv3TestEngine - trace" Section on FVP manual, but I still cannot find the mapping in this section. Actually I don't know how to "understand" the trace Section.

I also try to dump the FVP model but I can not find it. It only has SMMU configurations, but not this engine.

Can someone help me?

Sincerely, WANG Chenxu -- TF-A-Tests mailing list -- tf-a-tests@lists.trustedfirmware.org To unsubscribe send an email to tf-a-tests-leave@lists.trustedfirmware.org

Hi Chenxu,

I asked our models team about public documentation for the SMMUv3TestEngine. Notice the test cases you refer to were developed in context of testing the S-EL2 SMMU driver at component level, with test code running at S-EL1. You're importing such test code into EL3 so you might face issues as the code wasn't designed for this purpose.

Perhaps we can help you more efficiently, by explaining the use case you intend exercise.

Thanks, Olivier.

________________________________ From: Chenxu Wang via TF-A-Tests tf-a-tests@lists.trustedfirmware.org Sent: 17 December 2022 13:35 To: Madhukar Pappireddy Madhukar.Pappireddy@arm.com Cc: tf-a-tests@lists.trustedfirmware.org tf-a-tests@lists.trustedfirmware.org Subject: [Tf-a-tests] Re: Any manuals for SMMUv3 Test Engine?

Hi Madhukar,

I am looking for debugging my operations on this engine. I follow the codes in tf-a-tests and consider to replay them on arm-tf (e.g., in bl31 firmware). I want to copy the data in a region (0xb000_0000 - 0xb000_0fff) to another region (0xb000_1000 - 0xb000_1fff). Here I only use one frame buffer.

Thus, I write:

/* Base address of user and PRIV frames in SMMUv3TestEngine */ #define USR_BASE_FRAME ULL(0x2BFE0000) #define PRIV_BASE_FRAME ULL(0x2BFF0000)

uint64_t begin_addr=0xb0000000; uint64_t end_addr=0xb0000000+0x1000-1U; uint64_t dest_addr=0xb0001000;

/* Initiate DMA sequence */ mmio_write_32(PRIV_BASE_FRAME+PCTRL_OFF, 0); mmio_write_32(PRIV_BASE_FRAME+DOWNSTREAM_PORT_OFF, 0); mmio_write_32(PRIV_BASE_FRAME+STREAM_ID_OFF, 0); mmio_write_32(PRIV_BASE_FRAME+SUBSTREAM_ID_OFF, NO_SUBSTREAMID);

mmio_write_32(USR_BASE_FRAME+UCTRL_OFF, 0); mmio_write_32(USR_BASE_FRAME+SEED_OFF, 0); mmio_write_64(USR_BASE_FRAME+BEGIN_OFF, begin_addr); mmio_write_64(USR_BASE_FRAME+END_CTRL_OFF, end_addr);

/* Legal values for stride: 1 and any multiples of 8 */ mmio_write_64(USR_BASE_FRAME+STRIDE_OFF, 1); mmio_write_64(USR_BASE_FRAME+UDATA_OFF, dest_addr); mmio_write_32(USR_BASE_FRAME+CMD_OFF, ENGINE_MEMCPY);

But when I read the status of the USR_BASE_FRAME+CMD_OFF, I get an ENGINE_ERROR (before submitting, it is ENGINE_HALTED). I may feel difficult to debug without an available manual, can you help me to debug?

Sincerely, WANG Chenxu

Madhukar Pappireddy Madhukar.Pappireddy@arm.com 于2022年12月17日周六 04:05写道：

Hi,

The Base Platform Fast Model from Arm provides a SMMUv3TestEngine component with a control region at 0x002bfe0000-0x002bffFFFF. This component is a traffic generator that acts as a (secure) device upstream of the SMMUv3. We developed the test in the tf-a-tests repo by leveraging this test engine after referring to some documentation in files internal to Arm. Unfortunately, I could not find any detailed upstream documentation for this module.

Software running at lower ELs such as S-EL1 can generate memory transactions on the bus, by writing to the control pages, to mimic workloads such as memcpy. Is there anything that you are looking for in particular with this testengine?

Thanks, Madhukar

-----Original Message----- From: Chenxu Wang via TF-A-Tests tf-a-tests@lists.trustedfirmware.org Sent: Friday, December 16, 2022 9:55 AM To: tf-a-tests@lists.trustedfirmware.org Subject: [Tf-a-tests] Any manuals for SMMUv3 Test Engine?

Hi All,

I find that in spm/cactus/cactus_tests/smmuv3_test_engine.h, the tf-a-tests clearly shows some MMIO interfaces for the SMMUv3 Test Engine. But, I need help finding a manual about these MMIO interfaces. For example, in this .h file, it says the offset of the start address is in 0x28 (BEGIN_OFF), but I cannot find which manual defines it. It refers to the "SMMUv3TestEngine - trace" Section on FVP manual, but I still cannot find the mapping in this section. Actually I don't know how to "understand" the trace Section.

I also try to dump the FVP model but I can not find it. It only has SMMU configurations, but not this engine.

Can someone help me?

Sincerely, WANG Chenxu -- TF-A-Tests mailing list -- tf-a-tests@lists.trustedfirmware.org To unsubscribe send an email to tf-a-tests-leave@lists.trustedfirmware.org

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