Could you add a new gicd_set_ctlr() API to set GICD_CTLR to wait until RWP becomes zero? - Hafnium

28 Jun 2024

Hi ,
Could you add below patch to gicv3_helpers.h?

--- a/src/arch/aarch64/plat/interrupts/gicv3_helpers.h
+++ b/src/arch/aarch64/plat/interrupts/gicv3_helpers.h
@@ -203,6 +203,16 @@ static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
        }
 }
+static inline void gicd_set_ctlr(uintptr_t base,
+                               unsigned int bitmap,
+                               unsigned int rwp)
+{
+       gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
+       if (rwp != 0U) {
+               gicd_wait_for_pending_write(base);
+       }
+}
+
 static inline uint32_t gicd_read_pidr2(uintptr_t base)
 {
        return io_read32(IO32_C(base + GICD_PIDR2_GICV3));
The existed gicd_write_ctlr() just write the GICD_CTLR, but from GIC spec, if write GICD_CTLR, it needs to wait the RWP bit becomes zero.
Therefore, I think the gicd_set_ctlr() function of tf-a is a good choice.
I tried to push this patch to https://review.trustedfirmware.org/, but I encountered below error.
error: RPC failed; HTTP 403 curl 22 The requested URL returned error: 403

    