Hi all,
I want to find a register which will specifically control the Secure Stage 2 translation. But Arm document does not provide it.
I find that a register, called HCR_EL2, will control the Stage 2 translation. But the document didn't mention which secure type it will control. Thus, does the Non-secure hypervisor (like KVM) influence the Secure Stage-2 address translation? For example, disabling it through HCR_EL2?
Sincerely, WANG Chenxu