Hi Olivier,
Here are my answers.
[OD1] I am trying to extend the Hafnium to access some NS DRAM space (e.g. 0x80000000 - 0xFF000000) to achieve some communication between S and NS world. I think the Secure World can access the memory or registers, isn't it? I am using FVP.
[OD2] It tells a sync external abort, specifically a data abort, and not on translation table walk. (ESR=0x9600_0210, EC=0x25)
[OD3] Sorry, maybe this part is not related to my problem. So please ignore it. In TZASC it allows both S and NS to access the DRAM.
[OD4] Actually, I try a brute-force approach, i.e., adding this in bool mm_init(struct mpool *ppool) function. mm_identity_map(stage1_locked, pa_init(0x80000000),pa_init(0xFF000000),MM_MODE_R | MM_MODE_W, ppool); But I still fail to access the DRAM space.
Sincerely, Wang Chenxu
Olivier Deprez Olivier.Deprez@arm.com 于2021年10月5日周二 下午4:56写道：
Hi,
See answers below.
Regards, Olivier.
From: Hafnium hafnium-bounces@lists.trustedfirmware.org on behalf of Chenxu Wang via Hafnium hafnium@lists.trustedfirmware.org Sent: 05 October 2021 08:53 To: hafnium@lists.trustedfirmware.org Subject: [Hafnium] How to allow Hafnium to access a DRAM address space
Hi all,
I try to use Hafnium (deployed in SEL2) to access a DRAM address, e.g. 0xa000_0000, but failed.
[OD] Why is Hafnium supposed to access this DRAM address on your system? If possible can you tell more about the platform used? Hafnium accesses its own text, data, bss sections and sets up VMs/secure partitions environments (in Trusted DRAM on FVP). It is not supposed to map and access an arbitrary region (apart by using well defined FF-A interfaces).
I think the TTBR0_EL2 does not map this address space, or something wrong with TZASC.
[OD] What is the type of error hit when accessing this address (sync abort, serror, ...) ?
To solve this problem, I first add the DRAM region in TZASC and TTBR0_EL3 (by modifying TF-A), and EL3 can access this address. But Hafnium cannot read or write it.
[OD] Is the mentioned region marked secure or non-secure? Is it a kind of shared buffer with another SW entity?
So, must I modify the .S files in Hafnium to add a page mapping to the DRAM space? Can I add this page in some C files? Or should I do something else?
[OD] It's possible to map a region in the Hypervisor/SPMC EL2 Stage-1 translation regime through identity map functions, but as said there must be a well thought design decision to do so, or just use FF-A interfaces. Can you provide a rationale for this design?
Sincerely, Wang Chenxu -- Hafnium mailing list Hafnium@lists.trustedfirmware.org https://lists.trustedfirmware.org/mailman/listinfo/hafnium