I might be mistaken, but since the linking happens in TF-M, TF-M must be aware of this area? Anyway, I’m just wondering if someone knows how this works. I’ll try to ask in psa-arch-tests as well.

Thanks a lot for the link!

From: David Hu <David.Hu@arm.com>
Sent: Wednesday, September 9, 2020 10:04
To: Rønningstad, Øyvind <Oyvind.Ronningstad@nordicsemi.no>
Cc: tf-m@lists.trustedfirmware.org
Subject: RE: PSA tests: NVMEM section

Hi Øyvind,

IMOO, such a NVME area is psa-arch-tests dedicated requirement, instead of TF-M implementation or FF-M definitions. I’d suggest to ask for more details in https://github.com/ARM-software/psa-arch-tests/.

FYI a patch from psa-arch-test to enable such a NVME area in TF-M: https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/3360

Best regards,

Hu Ziji

From: TF-M <tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Rønningstad, Øyvind via TF-M
Sent: Wednesday, September 9, 2020 3:48 PM
To: tf-m@lists.trustedfirmware.org
Subject: [TF-M] PSA tests: NVMEM section

According to psa-arch-tests[1] the tests need an NVMEM area to write its states to.

“Non-volatile memory support to preserve test status over watchdog timer reset. Each byte of this region must be initialised to FF at power on reset.”

I could not find any code that does this in the TF-M or PSA repos. How do other platforms reserve and manage this 1k area.

[1]: https://github.com/ARM-software/psa-arch-tests/blob/master/api-tests/docs/porting_guide_dev_apis.md