Hi David,

One of our observation is that for Medium profile, some ciphers are disabled in the medcrypto portion through the config file (tfm_mbedcrypto_config_profile_medium.h). However, the CC312 components appears to be generating libraries that are disabled in mbedcrypto. One such example is the object file: cc_ecpki_domain_secp521r1.o generated for medium profile.

Wondering if this is expected or just an overlooked escape. I am assuming all ciphers not enabled in mbedcrypto portion should NOT have corresponding cc312 components, to help optimize the image sizes.

thanks

Suresh Marisetty

Infineon Semiconductor Corporation

From: David Hu <David.Hu@arm.com>
Sent: Sunday, July 4, 2021 11:37 PM
To: Marisetty Suresh (CYSC CSS ICW SW SSE) <Suresh.Marisetty@infineon.com>; Mark Horvath <Mark.Horvath@arm.com>
Cc: nd <nd@arm.com>; tf-m@lists.trustedfirmware.org
Subject: RE: Questions on Musca-B1 SE implementation - code size analysis

Caution: This e-mail originated outside Infineon Technologies. Do not click on links or open attachments unless you validate it is safe.

Hi Suresh,

Please check t Profile Medium and Profile Large design documents below. The ciphers supported are listed in the document.

Profile Medium: https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/profiles/tfm_profile_medium.html
Profile Large: https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/profiles/tfm_profile_large.html

I don’t think the software countermeasures against physical attacks are enabled in Musca-B1 SE, by default. Mark, please correct me if I misunderstand it.

TF-M implements a Fault Inject Hardening (FIH) library as software countermeasure to mitigate physical attacks.

FIH is enabled as Medium Profile in Profile Large by default. You can set `TFM_FIH_PROFILE` as OFF to disable FIH features.

FIH is not implemented by mebd TLS or CC312. It consists of protections of TF-M SPM critical routine and platform specific isolation configuration.

Please check FIH design document: https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/tfm_physical_attack_mitigation.html

Compared to Profile Medium, Profile Large enables more cryptographic algorithms support and FIH library.

It may also include more configurations of higher isolation.

Best regards,

Hu Ziji

From: TF-M <tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Suresh Marisetty via TF-M
Sent: Sunday, July 4, 2021 2:26 AM
To: Mark Horvath <Mark.Horvath@arm.com>; tf-m@lists.trustedfirmware.org
Cc: nd <nd@arm.com>
Subject: [TF-M] Questions on Musca-B1 SE implementation - code size analysis

Hi Mark,

Wondering if someone can provide more visibility in the following in regards to the SE build with profile medium and large:

What ciphers are supported in medium vs. large (I see the size of the code bloats up almost twice from 30 to 60K approx) – observation from size of libmbedcrypto and libcrypto_service_cc312 – any clear documentation on this or a link would be helpful (besides code review)
When the SE is built for the large profile, assume it also includes “Software countermeasures against physical attacks” since it is offloading to the CC-312

Is there a way to build the large profile without physical attack counter-measures?
While library are these countermeasures implemented in (libmbed or lib_cc312)?

On our initial analysis, for a medium profile these two libraries appears to be 30K-33K in size each and is this in the right ballpark? (with minsizerel)

I assume the code size increase is due to additional cipher support + physical attack countermeasures. Correct me otherwise.

thanks

Suresh Marisetty

Infineon Semiconductor Corporation

From: Mark Horvath <Mark.Horvath@arm.com>
Sent: Friday, May 14, 2021 5:30 AM
To: Marisetty Suresh (CYSC CSS ICW SW SSE) <Suresh.Marisetty@infineon.com>; tf-m@lists.trustedfirmware.org
Cc: nd <nd@arm.com>
Subject: Re: Questions on Musca-B1 SE implementation

Caution: This e-mail originated outside Infineon Technologies. Do not click on links or open attachments unless you validate it is safe.

Hi Suresh,

Yes, by default the cc312 acceleration is turned on at build time for SE, and the algorithms will be handled by HW instead of the SW implementation. If you would like to use SW crypto instead you can pass the HW_ACCELERATOR="OFF" flag to cmake when building the SE TF-M instance.

And here are the TF-M image sizes as of now with GCC in release mode:

SE: ~185 KiB code flash and ~63 KiB RAM

Host: ~22 KiB code flash and ~16 KiB RAM

(a few more KiB needed for the images in flash for image header and trailer if loaded by mcuboot)

Best regards,

Mark

From: David Hu <David.Hu@arm.com>
Sent: Thursday, May 13, 2021 5:26 AM
To: Suresh.Marisetty@infineon.com <Suresh.Marisetty@infineon.com>; Tamas Ban <Tamas.Ban@arm.com>; tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org>; Mark Horvath <Mark.Horvath@arm.com>
Cc: nd <nd@arm.com>
Subject: RE: Questions on Musca-B1 SE implementation

Hi @Mark Horvath,

Could you please help take a look at the following questions about Musca-B1 SE?
Thanks 😊

Best regards,

Hu Ziji

From: TF-M <tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Suresh Marisetty via TF-M
Sent: Thursday, May 13, 2021 6:04 AM
To: Tamas Ban <Tamas.Ban@arm.com>; tf-m@lists.trustedfirmware.org
Cc: nd <nd@arm.com>
Subject: Re: [TF-M] Questions on Musca-B1 SE implementation

Hi Tamas,

The following is good information. A few questions:

Is it correct to state that for the SE, the PSA RoT services do not have any software Crypto implementation, but leverage from CC-312?
What is the size of the TFM on the host (M33) with only PSA RoT service proxy with redirection to SE
Just trying to understand the TFM image size requirements on M33 vs. SE
How much of the Flash region/code Executed In Place vs. execution out of SRAM (XIP)

thanks

Suresh Marisetty

Infineon Semiconductor Corporation

From: Tamas Ban <Tamas.Ban@arm.com>
Sent: Friday, April 30, 2021 12:40 AM
To: Marisetty Suresh (CYSC CSS ICW SW SSE) <Suresh.Marisetty@infineon.com>; tf-m@lists.trustedfirmware.org
Cc: nd <nd@arm.com>
Subject: RE: Questions on Musca-B1 SE implementation

Caution: This e-mail originated outside Infineon Technologies. Do not click on links or open attachments unless you validate it is safe.

Hi Suresh,

Here is a link how to build images to Musca-B1 SE:
https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/musca_b1/secure_enclave/readme.rst

I have built with GCC and MinSizeRel build type:

Profile Medium:

Memory region Used Size Region Size %age Used

FLASH: 101464 B 381 KB 26.01%

RAM: 61304 B 64 KB 93.54%

[100%] Built target tfm_s

Profile Large:
Memory region Used Size Region Size %age Used

FLASH: 170448 B 381 KB 43.69%

RAM: 62980 B 64 KB 96.10%

[ 97%] Built target tfm_s

The profiles means different capabilities of TF-M, they were introduced to support constrained devices as well, with limited capability.

There is a detailed description about the profiles here:

https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/docs/technical_references/profiles

BR,

Tamas

From: TF-M <tf-m-bounces@lists.trustedfirmware.org> On Behalf Of Suresh Marisetty via TF-M
Sent: 2021. április 29., csütörtök 21:49
To: tf-m@lists.trustedfirmware.org
Subject: [TF-M] Questions on Musca-B1 SE implementation

I am following up on a question that came up on the TFM Core and MCUBoot image sizes that is built for SE on Musca-B1.

We are trying to figure out the resource requirements for SE, to be able to host the TF-M as suggested in the slides below. Wondering if anyone throw more light on the RAM/FLASH requirements for it.

Also, does the TFM profile small/medium/large map to this at all or is it different from them. Also, what’s are the estimated latencies of boot on SE with all the Flash accesses, etc.

https://www.trustedfirmware.org/docs/Musca-B1-Secure-Enclave-Solution.pdf

https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/musca_b1/secure_enclave

Any info on this would be appreciated.

thanks

Suresh Marisetty

Infineon Semiconductor Corporation