Hi, All

 

Patches for FPU support in TF-M are ready for review now. Looking for your comments!

FPU here refers to Float-point unit for Arm-M profile architecture.

  1. FPU support in TF-M
    1. Support platforms: all platforms with FPU available. Current patches are developed on arm musca_s1 board as example.
    2. After necessary settings in TF-M, it is configurable that FPU can be enabled in SPE or NSPE, or both sides.

System developer can activate FPU feature on a platform by setting those flags in CMake command line.

                                                               i.      Enable FP in secure side: -DTFM_SYSTEM_FP= 0-software, 1-hybird, 2-hardware

                                                             ii.      Enable FP in non-secure side: -DTFM_SYSTEM_FP_NS= 0-software, 1-hybird, 2-hardware

Also lazy stacking feature can be enabled/disabled in SPE or NSPE separately.

                                                           iii.      Enable lazy stacking in secure side: -DTFM_LAZY_FP=ON

                                                           iv.      Enable lazy stacking in non-secure side: -DTFM_LAZY_FP_NS=ON

    1. The secure service developer/application developer does need to know the FPU setting details, they can just compile their program with proper toolchain flags to take advantage of FPU.

The tested toolchains are: GNU Arm embedded toolchain and Arm Compiler. Other toolchain has FPU support should also work but needs test report from partners.

Three floating-point Application Binary Interface (ABI) types of mentioned toolchain are tested: software, hybrid, and hardware option.

    1. Support isolation level 1,2,3.
    2. FPU needs to be available in your platform if you want to take the advantage of a hardware FPU.

Please check your platform hardware specification whether FPU is available. Also need to check specification of toolchain whether the FPU architecture of your platform is supported.

FPU architecture can be specified by -DTFM_FP_ARCH in CMake command line.

  1. Notes:
    1. As FF-M alignment is one of our design goals, it only supports IPC partitions at current stage.
    2. The security mechanism is designed based on ARMv8-M Mainline and later.
    3. To simplify the scenarios, we defined several guidelines that no involving FPU usage inside an interrupt handler, including deprivileged handler in one Partition.

This can be fine-tuned later if there are requirements that insists a FPU support in handler mode.

    1. In general, FPU is commonly available on a Armv8.0-M mainline. Please check your platform specification and report exception cases if seen.
  1. For the VLLDM instruction security vulnerability of FPU, to mitigate this security vulnerability, it is required to recompile the secure image with compilers that has the software workaround implemented.

For more information, please check https://developer.arm.com/support/arm-security-updates/vlldm-instruction-security-vulnerability.

  1. Those patches will be merged in 4-6 weeks if there is no big issue found.

 

tf-m repo:

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11688 FP context protection

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11689 Add FPU support for gnu arm embedded toolchain

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11690 Configure non-secrue timer for FPU test

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11691 Add FPU support design document

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11692 Output support for FP numbers

https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/11693 FPU support for Armclang compiler

 

tf-m-tests repo:

https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/11684 Add FPU support

https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/11685 Adding FPU test cases

https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/11686 Adding FPU non-secure interrupt test case

https://review.trustedfirmware.org/c/TF-M/tf-m-tests/+/11687 Printf support for FP numbers

 

Best Regards

Feder