Hi,

Do you mind sharing your commands/configs of building TF-M?

May I know if you downloaded a whole NS+S image or separated images to MSP2?

Best regards,

Hu Ziji

From: Antonio De Angelis via TF-M <tf-m@lists.trustedfirmware.org>
Date: Friday, October 6, 2023 at 02:11
To: capablegh@gmail.com <capablegh@gmail.com>, tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org>, nd <nd@arm.com>
Subject: [TF-M] Re: Building TF-M for ARM reference SoC/boards MPS2/MPS3 and Musca S1

Hi, 

The reference designs hosted on the upstream repo, for MPS2 (AN521) for example already work like this (the other core is disabled) . I believe that the choice of the topology is determined by the integration setup, so this question I believe is more for some Zephyr-specific mailing list, or if there is any Zephyr dev reading this list they could chime in. 

Thanks, 

Antonio 

Sent from Outlook for Android

---

From: capablegh--- via TF-M <tf-m@lists.trustedfirmware.org>
Sent: Thursday, October 5, 2023 12:34:54 pm
To: tf-m@lists.trustedfirmware.org <tf-m@lists.trustedfirmware.org>
Subject: [TF-M] Building TF-M for ARM reference SoC/boards MPS2/MPS3 and Musca S1

Hello.

The ARM MPS2/MPS3 have Cortex M33 two processor configuration. I am building TF-M under the Zephyr OS setup. From the build it appears that the secure (TF-M) and non-secure (Zephyr OS and app) are bound and executed on separate CPUs. Assuming that two CPUs are used, in the build, is there a way to force using same one CPU for TF-M and Zephyr/app, while disabling the second CPU?

Thanks.
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