Hi Suresh,
Here is a link how to build images to Musca-B1 SE:
https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/musca_b1/secure_enclave/readme.rst
I have built with GCC and MinSizeRel build type:
Profile Medium:
Memory region Used Size Region Size %age Used
FLASH: 101464 B 381 KB 26.01%
RAM: 61304 B 64 KB 93.54%
[100%] Built target tfm_s
Profile Large:
Memory region Used Size Region Size %age Used
FLASH: 170448 B 381 KB 43.69%
RAM: 62980 B 64 KB 96.10%
[ 97%] Built target tfm_s
The profiles means different capabilities of TF-M, they were introduced to support constrained devices as well, with limited capability.
There is a detailed description about the profiles here:
https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/docs/technical_references/profiles
BR,
Tamas
From: TF-M <tf-m-bounces@lists.trustedfirmware.org>
On Behalf Of Suresh Marisetty via TF-M
Sent: 2021. április 29., csütörtök 21:49
To: tf-m@lists.trustedfirmware.org
Subject: [TF-M] Questions on Musca-B1 SE implementation
I am following up on a question that came up on the TFM Core and MCUBoot image sizes that is built for SE on Musca-B1.
We are trying to figure out the resource requirements for SE, to be able to host the TF-M as suggested in the slides below. Wondering if anyone throw more light on the RAM/FLASH requirements for it.
Also, does the TFM profile small/medium/large map to this at all or is it different from them. Also, what’s are the estimated latencies of boot on SE with all the Flash accesses, etc.
https://www.trustedfirmware.org/docs/Musca-B1-Secure-Enclave-Solution.pdf
Any info on this would be appreciated.
thanks
Suresh Marisetty
Infineon Semiconductor Corporation