The least significant 128 bits of SVE vector registers are physically the same registers as those used by FP/NEON. Also that saving and restoring just the FP/NEON without also saving and restoring SVE predicate registers might corrupt predicate registers. Other than that, the maximum size of SVE vector registers (2048 bits) is too large to reasonably fit in cpu_context_t. One way to work around this size problem would be to have the platform implementation supply memory buffer used to save and restore SVE registers.

Other implication of large size of these registers is that unconditionally saving and restoring will take more time at each world switch. However, most edge CPU cores (Cortex-X2,
Cortex-X3, Cortex-A510, Cortex-A710, Cortex-A715, Hayes, Hunter and Hunter ELP ) have SVE vector length of 128 bits. So on those cores the overhead of world switch won't be much different from the overhead of FP regs during world switch.

Thanks,

Okash