Hi Feifan Qian,
Trapping GPF to EL3 is permitted by the architecture, however I don't believe TF-A provides such option.
In general for TF-A's reference software stacks, a GPF is trapped first at EL2 (hence SCR_EL3.GPF=0).
E.g.
In a system implementing RME, the RMM (@ R-EL2) traps a GPF occurring in an R-EL1/0 Realm (or R-EL2 itself).
Similarly, in the secure world, the SPM (@ S-EL2) traps a GPF occurring in a S-EL1/0 secure partition (or S-EL2 itself).
Regards,
Olivier.
From: 钱非凡 <qianfeifan@iie.ac.cn>
Sent: 01 July 2024 08:52
To: tf-a-owner@lists.trustedfirmware.org <tf-a-owner@lists.trustedfirmware.org>
Subject: Questions about the Fault Handling of GPFs
Dear experts,
I have been learning the Fault Handling of the Granule Protection
Fault in Arm CCA. Upon studying the Arm Document, I discovered that the
GPF bit in the SCR_EL3 register controls whether the fault handling of
GPFs occurs in EL3 or not. In addition, I noted that
`include/arch/aarch64/arch.h` defines a macro `#define SCR_GPF_BIT
(UL(1) << 48)`, yet I could not find any reference to this macro in the
source code.
I want to know that whether ATF has implemented the fault handling
of GPFs or if this is a feature to be expected in the future. If its
not, how can I implement this. Any guidance or advice you could provide
would be greatly appreciated.
Sincerely,
Feifan Qian